This invention relates to a sense-amplifier for a metal oxide silicon chip memory device and more particularly to a sense-amplifier for detecting complementary signals produced by a static memory cell comprising one of an array of such cells in a semiconductor device.
In the readout process of a static memory circuit the simultaneous selection of an address line and a bit column produces a differential voltage on the selected column bit lines that must be detected and amplified to provide the proper output signal. It is desirable, if not imperative that such sense-amplifiers utilize a minimum of chip area, operate with a minimum of power and yet with high relative speed. A particular requirement for a sense-amplifier is that it be highly sensitive to voltage fluctuations in the bit lines and yet immune to interference or cross-talk between bit lines of other columns so as to enable the accurate and reliable readout of stored data. In certain prior art sense-amplifiers column selection was done by adding a selection transistor in series with a pair of sense amplifier transistors, each of which was connected to one output bus line. The gate of each transistor of the latter pair was connected directly to one of the bit lines. One disadvantage of connecting the bit lines to the gates of the transistors in this arrangement was that a relatively small impedance differential resulted between the output bus lines and ground potential. This reduced the signal output level of the sense-amplifier. Another disadvantage with this prior art arrangement was that with the selection transistor stacked in series with the sense amplifier-transistors the impedance from the output bus lines to ground was increased by the impedance of the selection transistor. This required higher pull-up impedances for the output bus lines which in turn reduced the inherent speed of the memory device.